Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6852635B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Dec 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be “bottomless,” thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.