Non-volatile memory architecture and method thereof
US6853586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | May 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array of one-transistor (1T) SONOS bit cells in a common-source architecture is used in conjunction with a reverse read technique to reduce the effect of read disturb. Bit line voltage in the array, during read operation, is constrained to a Vt or less, relative to the control gate, so that read disturb is limited. When information is programmed into a bit cell in the array, the bit line is used as a drain, which has the effect of concentrating charge toward the bitline end of the SONOS transistor. When information is read from a bit cell in the array, the bit line of the selected bit cell is used as a source, instead of a drain. That reversal gives a larger Vt contrast between a 0 and a 1 than a forward read, for a given amount of stored charge. Using the bit line in this manner limits the electric field to which the oxide of the bit cell is exposed, thereby lessening the amount of read disturb, while also improving the magnitude of the read mode signal and, therefore, improving overall tolerance of the read disturb effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.