Self aligned double gate transistor having a strained channel region and process therefor
US6855982B1 · kind B1 · utility
76Cited by
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20Claims
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Key dates
| Filing date | Feb 2, 2004 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Feb 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
Abstract
A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.