High density semiconductor memory cell and memory array using a single transistor
US6856540B2 · kind B2 · utility
37Cited by
65References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2003 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Jul 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+region in the substrate underlying the gate of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.