Method of fabricating semiconductor integrated circuit device
US6858484B2 · kind B2 · utility
2Cited by
19References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Nov 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.