Method for aligning and exposing a semiconductor wafer

US6861331B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Martin Rössiger · Dresden, DE
• Thorsten Schedel · Dresden, DE
• Jens Stäcker · Eindhoven, NL

Key dates

• Filing date: Oct 16, 2003
• Grant date: Mar 1, 2005
• Expiry date: Oct 16, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/975
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the locational position of alignment marks and/or oblique measurement structures. Measurement structures are formed preferably in the frame region of product wafers comprising electrical circuits to be formed and their locational positions before and after the effect of the process that has an effect are compared individually for purpose of determining the positional displacement for each relevant exposure field. From this there is determined either directly a “shot”-fine correction value for the individual exposure or at least one nonlinear function for the correction in dependence on the position of the measurement structures on the wafer. The corrections are applied to the exposure fields after alignment to the alignment marks overformed by the process in dependence on their position on the wafer.