Apparatus and methods for determining and localization of failures in test structures using voltage contrast
US6861666B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Feb 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/307
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is test structure that can be fabricated with minimal photolithography masking steps and in which defects may be localized to specific layers. Mechanisms for fabricating such test structures are also provided. In one embodiment, a semiconductor test structure suitable for a voltage contrast inspection is provided. The test structure includes one or more test layers corresponding to one or more product layers selected from a plurality of product layers of an integrated circuit (IC) product structure. The number of the selected one or more test layers is less than a total number of the plurality of product layers of the product structure, and the test layers include at least a first portion that is designed to have a first potential during the voltage contrast inspection and a second portion that is designed to have a second potential during the voltage contrast inspection. The first potential differs from the second potential. The selected one or more test layers which correspond to product layers are selected from the plurality of product layers such that defects found in the test layers of the test structure during the voltage contrast inspection represent a prediction o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.