Enhanced silicidation of polysilicon gate electrodes

US6867130B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Olov Karlsson · San Jose, US
• Simon S. Chan · Saratoga, US
• William G. En · Sunnyvale, US
• Mark W. Michael · Cedar Park, US

Key dates

• Filing date: May 28, 2003
• Grant date: Mar 15, 2005
• Expiry date: May 28, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.