Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials

US6869542B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Sadanand V. Desphande · Fishkill, US
• David M. Dobuzinsky · New Windsor, US
• Arpan Mahorowala · West Linn, US
• Tina Wagner · Newburgh, US
• Richard S. Wise · Beacon, US

Key dates

• Filing date: Mar 12, 2003
• Grant date: Mar 22, 2005
• Expiry date: Mar 22, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31116
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF4, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (−20 to 60°).