Method of fabricating trench MIS device with graduated gate oxide layer

US6875657B2 · kind B2 · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Christiana Yue · Milpitas, US
• Mohamed N. Darwish · Campbell, US
• Frederick P. Giles · San Jose, US
• Kam Hong Lui · Santa Clara, US
• Kuo-In Chen · Los Altos, US
• Kyle Terrill · Santa Clara, US
• Deva Pattanayak · Saratoga, US

Key dates

• Filing date: Mar 26, 2002
• Grant date: Apr 5, 2005
• Expiry date: Mar 26, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/157
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird's beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.