Semiconductor package with increased number of input and output pins
US6876068B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | May 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads. At least portions of the die paddle, the first and second leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the first leads being exposed in a common exterior surface of the package body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.