Electroplating using DC current interruption and variable rotation rate

US6884335B2 · kind B2 · utility

Assignee

• Novellus Systems, Inc. · US

Inventors

• Eric G. Webb · West Linn, US
• Jonathan D. Reid · Sherwood, US
• John Sukamto · Lake Oswego, US
• Sesha Varadarajan · Wilsonville, US
• Margolita M. Pollack · Beaverton, US
• Bryan L. Buckalew · Tualatin, US
• Tariq Majid · Wilsonville, US

Key dates

• Filing date: May 20, 2003
• Grant date: Apr 26, 2005
• Expiry date: Oct 21, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T428/12993
• WIPO field: Surface technology, coating
• WIPO sector: Chemistry

Abstract

A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.