Memory device having A P+ gate and thin bottom oxide and method of erasing same
US6885590B1 · kind B1 · utility
26Cited by
12References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2003 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Sep 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/687
Abstract
A non-volatile memory device includes a semiconductor substrate and an N-type source and drain within the substrate. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a thin bottom oxide layer. A P+ polysilicon electrode is formed over the ONO stack. The memory device is operative to perform a channel erase operation in which a pair of charge storing cells with the nitride layer are erased simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.