Sensing test circuit
US6885597B2 · kind B2 · utility
2Cited by
14References
39Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Sep 10, 2002 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Dec 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.