Patent · US Expired

Method and apparatus for localizing faults within a programmable logic device

US6889368B1 · kind B1 · utility

47Cited by

12References

16Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

David Mark · San Jose, US
Randy J. Simmons · San Jose, US
Min Luo · Beijing, CN

Key dates

Filing date	Oct 25, 2002
Grant date	May 3, 2005
Priority date	—
Expiry date	Jan 31, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318516
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Method and apparatus for localizing faults within an integrated circuit is described. For example, a programmable logic device (PLD) is configured with a test pattern. A test stimulus is applied to the test pattern. State data responsive to the test pattern is obtained. The state data may be obtained from a readback datastream generated by the PLD. The expected state data may be generated by a second PLD that is known to contain no faults. The state data is compared with expected state data to produce difference information. The difference information is used, or more particularly is iteratively generated, to localize a fault or faults within a unit under test.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.