Method of making a lead-free integrated circuit package
US6889429B2 · kind B2 · utility
24Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2001 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Feb 13, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.