Magnetoresistive random access memory device structures and methods for fabricating the same
US6890770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2004 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jul 6, 2024 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.