Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier
US6891231B2 · kind B2 · utility
7Cited by
10References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 13, 2001 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jun 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28194
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.