STI formation for vertical and planar transistors

US6893938B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Munir D. Naeem · Poughkeepsie, US
• Hiroyuki Akatsu · Yorktown Heights, US
• Byeong Y. Kim · Lagrangeville, US
• Rolf Weis · Dresden, DE
• David Mark Dobuzinksy · New Windsor, US
• Johnathan E. Faltermeier · San Jose, US

Key dates

• Filing date: Apr 21, 2003
• Grant date: May 17, 2005
• Expiry date: Aug 4, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3081
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.