Defect-minimizing, topology-independent planarization of process surfaces in semiconductor devices

US6893968B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Peter Lahnor · Dresden, DE
• Alexander William Simpson · Wappingers Falls, US

Key dates

• Filing date: Oct 10, 2002
• Grant date: May 17, 2005
• Expiry date: Jan 20, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76224
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.