Semiconductor integrated circuit device
US6894944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2003 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Sep 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldMaterials, metallurgy
- WIPO sectorChemistry
Abstract
To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.