Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same

US6900494B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Todd R. Abbott · Boise, US
• Mike Violette · Boise, US
• Zhongze Wang · San Diego, US
• Jigish D. Trevidi · Boise, US

Key dates

• Filing date: Feb 17, 2004
• Grant date: May 31, 2005
• Expiry date: Feb 17, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12

Abstract

The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.