Method for defining alignment marks in a semiconductor wafer
US6902986B2 · kind B2 · utility
6Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2002 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Jun 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F9/708
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A lithography and etching method for forming an alignment mark (104) and at least one device feature (such as a shallow trench 105) on a wafer (99) is provided. The etching process (18) comprises: a first etching step (1811) for pre-defining at least one alignment mark (103) and a second etching step (1812) for defining desired semiconductor device patterns (such as a shallow trench 105) on said wafer surface and completing said at least one alignment mark (104).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.