Trench MIS device with graduated gate oxide layer

US6903412B2 · kind B2 · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Mohamed N. Darwish · Campbell, US
• Christiana Yue · Milpitas, US
• Frederick P. Giles · San Jose, US
• Kam Hong Lui · Santa Clara, US
• Kuo-In Chen · Los Altos, US
• Kyle Terrill · Santa Clara, US
• Deva Pattanayak · Saratoga, US

Key dates

• Filing date: Mar 26, 2002
• Grant date: Jun 7, 2005
• Expiry date: Mar 26, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/157
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the body and drain regions intersects the trench in the transition region. This structure allows for a greater margin of error in the placement of the PN junction during the manufacture of the device, since the intersection between the PN junction can be located anywhere in the transition region. The MIS device also has improved breakdown characteristics.