Method of manufacturing a semiconductor device having an interconnect embedded in an insulating film
US6908847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2002 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Dec 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.