Method and apparatus for specifying addressability and bus connections in a logic design
US6910002B1 · kind B1 · utility
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13References
29Claims
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Key dates
| Filing date | Aug 23, 2000 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Jul 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.