Patent · US Expired

Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices

US6912778B2 · kind B2 · utility

79Cited by
15References
31Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 19, 2001
Grant dateJul 5, 2005
Priority date
Expiry dateJan 13, 2022

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10T29/49165
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A full-wafer probe card, a method for making the probe card and a full-wafer testing system are provided. The probe card includes test probes comprising cantilever elements configured and arranged with probe tips in a pattern corresponding to an array of bond pads of semiconductor dice residing on a device wafer. The probe card is desirably fabricated of the same material, such as silicon, as the device wafer to be tested. The cantilever elements may be fabricated from the material of the probe card substrate using known silicon micro-machining techniques including isotropic and anisotropic etching. Additionally, conductive feedthroughs or vias are formed through the probe card to electrically connect the probe tips with conductive pads on an opposing side of the substrate which interface with test contacts of external test circuitry. The conductive feedthroughs may be formed as coaxial structures, which help to minimize stray capacitance and inductance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.