Method for patterning a feature using a trimmed hardmask
US6913958B1 · kind B1 · utility
4Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2003 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | May 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed hardmask layer is preferably an amorphous carbon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.