Salicide formation method

US6916729B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Sunfei Fang · Lagrangeville, US
• Keith Kwong Hon Wong · Wappingers Falls, US
• Paul D. Agnello · Wappingers Falls, US
• Christian Lavoie · Ossining, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Chester T. Dziobkowski · Hopewell Junction, US
• Richard J. Murphy · Clinton Corners, US
• Patrick W. DeHaven · Poughkeepsie, US
• Nivo Rovedo · Lagrangeville, US
• Hsiang-Jen Huang · Poughkeepsie, US

Key dates

• Filing date: Apr 8, 2003
• Grant date: Jul 12, 2005
• Expiry date: Apr 10, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/28052
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.