Reducing effects of noise coupling in integrated circuits with memory arrays
US6920059B2 · kind B2 · utility
4Cited by
8References
43Claims
0Family size
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Key dates
| Filing date | Nov 29, 2002 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Jun 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.