Bilayer wafer-level underfill
US6924171B2 · kind B2 · utility
19Cited by
15References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2001 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Feb 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating microelectronic interconnection structures as well as the structures formed by the methods are disclosed which improve the manufacturing throughput for assembling flip chip semiconductor devices. The use of a bilayer of polymeric materials applied on the wafer prior to dicing eliminates the need for dispensing and curing underfill for each semiconductor at the package level, thereby improving manufacturing throughput and reducing cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.