Inventor · Keyano, QC, CA

David Danovitch

13Patents

7h-index

33Co-inventors

62Inventor score

Filing activity: Feb 13, 2001 → Sep 5, 2012

Most-cited inventions

Patent	Title	Area	Cited by	Status
US6924171B2	Bilayer wafer-level underfill	Electricity	19	Expired
US8202765B2	Achieving mechanical and thermal stability in a multi-chip package	Electricity	17	Active
US6819566B1	Grounding and thermal dissipation for integrated circuit packages	Electricity	15	Expired
US8421217B2	Achieving mechanical and thermal stability in a multi-chip package	Electricity	15	Active
US6893799B2	Dual-solder flip-chip solder bump	Electricity	14	Expired
US8290008B2	Silicon carrier optoelectronic packaging	Electricity	14	Active
US7473618B1	Temporary structure to reduce stress and warpage in a flip chip organic package	Electricity	13	Active
US8559474B2	Silicon carrier optoelectronic packaging	Electricity	6	Active
US7820483B2	Injection molded soldering process and arrangement for three-dimensional structures	Electricity	6	Active
US7538432B1	Temporary structure to reduce stress and warpage in a flip chip organic package	Electricity	4	Active
US7498198B2	Structure and method for stress reduction in flip chip microelectronic packages using underfill materials with spatially varying properties	Electricity	4	Active
US7952205B2	Injection molded soldering process and arrangement for three-dimensional structures	Electricity	2	Active
US7786588B2	Composite interconnect structure using injection molded solder technique	Electricity	1	Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.