Stack arrangement of a memory module

US6927484B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Jochen Thomas · Munich, DE
• Wolfgang Hetzel · Nattheim, DE

Key dates

• Filing date: Nov 4, 2003
• Grant date: Aug 9, 2005
• Expiry date: Dec 10, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19107
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A stack arrangement of discrete components includes a carrier substrate and at least two discrete components, e.g., memory chips. The carrier substrate has line conductor structures and contact pads. Each of the discrete components includes centrally disposed bond pads and a metallic coating, which is electrically connected to the centrally disposed bond pads. The metallic coating is disposed on an active surface area of each discrete component. A protective structure overlies a central region of the discrete component. In the preferred embodiment, the metallic coatings of each discrete component are identical. Preferably, the discrete components are stacked on the carrier substrate so as to have the same orientation, so that the protective structure serves as a spacer between the discrete components. Further, the metallic coating is electrically coupled to the carrier substrate.