Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift
US6929992B1 · kind B1 · utility
39Cited by
4References
4Claims
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Key dates
| Filing date | Dec 17, 2003 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Dec 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The threshold voltage shift exhibited by strained silicon NMOS devices is compensated with respect to the threshold voltages of PMOS devices formed on the same substrate by increasing the work function of the NMOS gates. The NMOS gate work function exceeds the PMOS gate work function so as to compensate for a difference in the respective NMOS and PMOS threshold voltages. The NMOS gates are preferably fully silicided while the PMOS gates are partially silicided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.