Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate

US6939781B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Randy D. Redd · Chandler, US
• Paul Fisher · Tempe, US
• Olin L. Hartin · Chandler, US
• Lawrence S. Klingbeil, Jr. · Chandler, US
• Ellen Lan · Chandler, US
• Hsin-Hua P. Li · Tainan, TW
• Charles E. Weitzel · Mesa, US

Key dates

• Filing date: Jun 27, 2003
• Grant date: Sep 6, 2005
• Expiry date: Jun 27, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/411

Abstract

In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (420) above the semiconductor substrate, a gate electrode (1120) above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate (210) above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer (310) above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer (910) between the gate electrode and the field plate and not located above the gate electrode or the field plate.