Preventive treatment method for a multilayer semiconductor wafer
US6939783B2 · kind B2 · utility
8Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2004 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Feb 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is to be subjected to a subsequent treatment. The method includes encapsulating the exposed lateral edge of the intermediate layer with a portion of the surface layer to prevent attack on the peripheral edge during the subsequent treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.