High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown
US6940751B2 · kind B2 · utility
60Cited by
64References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2004 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Mar 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, a gate dielectric of the transistor has a higher breakdown voltage near the source connected to the row wordline than its drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.