Test methodology for direct interconnect with multiple fan-outs
US6943581B1 · kind B1 · utility
10Cited by
12References
38Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 27, 2003 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Mar 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3172
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test cell and method of operation are disclosed. The test cell may be cascaded with other test cells to form a test structure that spans across any number of slices and/or tiles in a programmable logic device. The test structure behaves like a register, and may be used to test direct interconnects and any number their fan-out lines simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.