Methods of resource optimization in programmable logic devices to reduce test time
US6944809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Dec 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.