Low cost fabrication and assembly of lid for semiconductor devices
US6949398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Jul 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for encapsulating micromechanical elements or features on a substrate. In accordance with the method, a first substrate (111) is provided which has a patterned surface (113). A seed metallization (121) is then deposited onto the patterned surface, and a structural material layer (123), which preferably comprises copper, is electroplated onto the seed metallization. A solder (125), such as SnCu, is electroplated onto the metal layer, and the seed metallization, the structural material layer and the solder are removed from the first substrate as a cohesive structure (127), through the application of heat or by other suitable means, such that a negative replica of the patterned surface is imparted to the structure. The structure may then be placed on a second substrate (129) such that the solder is in contact with the second substrate, after which the solder is reflowed. Prior to reflow, the solder may be exposed to a fluorinated plasma, which forms a dry flux on the solder surface in the form of fluorinated metal oxides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.