Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device
US6949481B1 · kind B1 · utility
33Cited by
20References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Jan 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process for fabricating a semiconductor device including steps of providing a semiconductor substrate having formed thereon a semiconductor device; depositing over the semiconductor device a spacer layer, the spacer layer having a first hydrogen content; and applying a treatment to reduce the first hydrogen content to a second hydrogen content. The invention is particularly useful when applied to flash memory devices such as a charge trapping dielectric flash memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.