Efficient compression and application of deterministic patterns in a logic BIST architecture
US6950974B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2001 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Jan 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318558
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Deterministic ATPG test coverage is provided in a logic BIST architecture while reducing test application time and test data volume, as compared to deterministic ATPG patterns. The logic BIST architecture can include a PRPG shadow operatively coupled to a PRPG circuit. The PRPG shadow allows re-seeding of the PRPG circuit with zero cycle overhead. Two compressions can be provided. In a first compression, multiple tests for faults are compressed into one pattern. In a second compression, multiple deterministic ATPG patterns can be compressed into one seed. All patterns provided from the PRPG can be controlled by these seeds so that all care bits are properly set, while all other scan cells are set to pseudo-random values from the PRPG. In this manner, the PRPG can rapidly deliver highly pertinent data to the scan chains of the device under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.