Address generator for generating addresses for testing a circuit

US6957373B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Wolfgang Ernst · Munich, DE
• Justus Kuhn · Birkenfeld, DE
• Jens Luepke · Birkenfeld, DE
• Peter Poechmüller · Colchester, US
• Gunnar Krause · Munich, DE
• Jochen Mueller · Regensburg, DE
• Michael Schittenhelm · Poing, DE

Key dates

• Filing date: Mar 6, 2002
• Grant date: Oct 18, 2005
• Expiry date: Jun 15, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/20
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.