Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen
US6958511B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2003 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Dec 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process of fabricating multi-bit charge trapping dielectric flash memory device, including forming on a semiconductor substrate a bottom oxide layer to define a substrate/oxide interface, in which the bottom oxide layer includes a first oxygen concentration and a first nitrogen concentration; and adding a quantity of nitrogen to the bottom oxide layer, whereby the bottom oxide layer includes a first region adjacent the charge storage layer and a second region adjacent the substrate/oxide interface, the second region having a second oxygen concentration and a second nitrogen concentration, in which the second nitrogen concentration exceeds the first nitrogen concentration, provided that the second nitrogen concentration does not exceed the second oxygen concentration. In one embodiment, the first nitrogen concentration is substantially zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.