Dynamic optimization of latency and bandwidth on DRAM interfaces
US6963516B2 · kind B2 · utility
4Cited by
3References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.