Programmable logic device with redundant circuitry

US6965249B2 · kind B2 · utility

Assignee

• Altera Corporation · US

Inventors

• Christopher F. Lane · San Jose, US
• Ketan Zaveri · San Jose, US
• Hyun Yi · Sunnyvale, US
• Giles V. Powell · Alameda, US
• Paul Leventis · Toronto, CA
• David Jefferson · San Jose, US
• David Lewis · Toronto, CA
• Triet Nguyen · San Jose, US
• Vikram Santurkar · Fremont, US
• Michael Chan · Bedford, US
• Andy L. Lee · San Jose, US
• Brian Johnson · Boise, US
• David Cashman · Toronto, CA

Key dates

• Filing date: May 30, 2002
• Grant date: Nov 15, 2005
• Expiry date: Oct 21, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17744
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.