Patent · US Expired

Integrated semiconductor memory circuit and a method for operating the same

US6965535B2 · kind B2 · utility

0Cited by

4References

16Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Manfred Proell · Dorfen, DE
Stephan Schroeder · Munich, DE
Ralf Schneider · Birkenfeld, DE
Joerg Kliewer · Munich, DE

Key dates

Filing date	Dec 23, 2003
Grant date	Nov 15, 2005
Priority date	—
Expiry date	Feb 14, 2024

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and can be connected to a common local data line (LDQ) by means of a respective assigned CSL switch in response to a CSL signal and in which an MDQ/LDQ switch arrangement connects a main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal. In the case of the semiconductor memory, a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal with the MDQ/LDQ switch signal and thereby activates the CSL switches only in cell blocks in which a word line has been activated.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.