Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown
US6972986B2 · kind B2 · utility
67Cited by
94References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2004 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Mar 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.