Electronic component having stacked semiconductor chips in parallel, and a method for producing the component

US6977427B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Wolfgang Hetzel · Nattheim, DE
• Jochen Thomas · Munich, DE

Key dates

• Filing date: Nov 26, 2003
• Grant date: Dec 20, 2005
• Expiry date: Nov 26, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An electronic component has a chip stack with a first semiconductor chip, a second semiconductor chip, and a large number of flat conductors configured in between the first semiconductor chip and the a second semiconductor chip. The flat conductors have a central section on which the semiconductor chips are mounted. First bonding connections connect the first semiconductor chip to inner sections of the flat conductors. Second bonding connections connect the second semiconductor chip to transitional sections of the flat conductors. The outer sections of the flat conductors project out of a package.