Processor virtualization mechanism via an enhanced restoration of hard architected states
US6981083B2 · kind B2 · utility
18Cited by
17References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Dec 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.